This invention relates generally to static random access memories, and more particularly the invention relates to static random access memories using N-channel enhancement mode transistors.
The static random access memory (SRAM) typically employs cross-coupled transistors which are connected to load transistors. The common nodes of the load transistors and the cross-coupled transistors store data as bit and bit. The writing of data into the memory cell creates a voltage differential at the two nodes which is perpetuated by the circuitry. The conventional six transistor SRAM memory cell includes two word select transistors connected to the two memory nodes.
Heretofore, SRAMs employing MOS transistors have typically employed, complementary MOS transistor pairs with the P-channel transistors functioning as loads for the cross-coupled N-channel transistors. Such circuits consume low power, but the necessity of doped wells in forming the complementary transistor pair increases the size of the cell and increases the complexity of device fabrication. N-channel memory cells have been fabricated, and such cells are smaller in size than CMOS memory cells. However, the N-channel cells have heretofore utilized depletion mode transistors with enhancement mode cross-coupled transistors. The depletion mode device must be suitably biased to provide the requisite loads.
The present invention is directed to a novel SRAM memory cell employing N-channel enhancement mode transistors which is small in size and low in power consumption.